main clock
英 [meɪn klɒk]
美 [meɪn klɑːk]
网络 主时钟; 相当于内存的主频
双语例句
- The main spring of the alarm clock is broken.
闹钟的簧断了。 - The neat thing about this second clock is that it can override the main clock* and you should just flip into that new time zone in one day.
第二时钟最妙的地方就在于它可以覆盖我们的主时钟，也就是说你应该可以在一天之内将你的生物钟调整到一个新的时区。 - Our main products include door handle, floor spring, Center Clock of Glass Door, door closer, patch fitting, glass door hinge and stainless steel hinge etc.
主要产品有拉手、地弹簧、玻璃门中央锁、闭门器、门夹、玻璃合页及不锈合页等系列。 - The main buildings in that temple are then Daxiong Hall ( the main hall in each buddhist temple), the Sutra Hall, the Clock Tower, the in script ion "Midnight Bells", the first floor of Maple River.
寒山寺中的主要景点有大雄宝殿、藏经楼、钟楼、碑文《枫桥夜泊》、枫江第一楼。 - The importance of the clock synchronization in the parallel distributed system is given, and three main methods for the clock synchronization are introduced.
叙述了并行分布式系统中时钟同步的重要性，并介绍了完成时钟同步的三种主要方法。 - Because the demands of high performance and low cost are now the main challenges for SoC design, the design of phase-locked loops ( PLLs) used as clock generators on chip becomes very critical.
由于高性能、低成本已成为SoC设计的主要挑战，作为片上时钟发生器锁相环的设计变得非常关键。 - Moreover, it completes the main controlling program and also realizes the clock setting, the keyboard interrupt service subprogram and the detection procedures of infrared and collision sensors.
并实现了主控程序及时钟设定、键盘中断服务、红外、碰撞传感器检测等子程序。 - Exploration for the Main Factor of the Rate Change of Industrial Cesium Clock
工业铯钟速率变化主要因素的探讨 - In this paper, the design of a specific chip for circuit emulation based on IP is put forward and realized and the main functional modules and the key algorithms including an all-digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail.
文章根据相关标准提出并实现了一种电路仿真专用芯片的设计方案，并对其中主要功能模块和关键算法作出了详细说明，包括一种全数字的自适应时钟恢复方法、动态深度缓冲算法等。 - Lastly this article briefly discusses the main application demands and developing trends of atom clock.
最后简述了原子钟的主要应用需求与发展趋势。 - It uses serial bus, i.e. there are only two lines to realize the communication between the main controller and the peripheral equipment, one is clock line ( SCL), and the other is data line ( SDL).
它采用串行总线，主控器与外围器件仅靠两条线进行信息传输，一条称为时钟线（SCL），另一条位数据线（SDA）。 - The article mainly discusses the physical principle, performance, working and application fields and recent research devel-opment of several main atom frequency standards such as Hydrogen, Rubidium, Cesium atom clock, etc.
本文主要介绍了氢钟、铷钟、铯钟等几种主要原子频标的物理工作原理、性能、工作与应用领域与研究进展； - Real-time clock/ calendar IC is the main chip of the clock systematic unit in the micro-control system.
实时时钟/日历芯片是构成微控制系统里时钟系统单元的主芯片。 - The main circuits include a trans-impedance amplifier ( TIA), a limiting amplifier, a clock and data recovery ( CDR) unit, and a ( 1 ∶ 4) demultiplexer ( DEMUX).
主要电路包括前置放大、限幅放大、时钟恢复、数据判决和1∶4分接。 - The Time Keeping System can be divided into three subsystems: The main ( clock, time transfer and time comparison system), the accessorial ( environment monitoring and controlling system) and the power supply system.
守时系统按其功能和工作的性质可分为主（原子钟、时间传递和比对系统）、辅（温湿度、电压环境监控系统）、外（电源系统）三个子系统。 - The write-operation of SDRAM is started by the output clock of image-sensor, and synchronized by the SDRAM main clock. The DSP is informed by CPLD when one frame image has been acquired.
图像缓存过程由DSP启动，在缓存过程中，SDRAM写操作首先被图像传感器的输出时钟触发，然后由SDRAM的主时钟进行同步，在一帧图像采集完成后CPLD通知DSP图像采集结束。 - We design the system from the investigation. The hard ware of the traffic signal control system bases on time distributing can divide into: main module, input and display module, clock module, output module, LED display module, memory module and communication module.
由调查结果得出系统所要实现的基本功能，按功能，将系统在硬件组成上分为主控模块、输入及显示模块、时钟模块、输出模块、放大模块、LED显示模块、存储模块、通讯模块。 - The main method in design of signal collection circuit, temperature detection circuit, real-time clock circuit and the hardware and software of Profibus-DP interface module were described. And the algorithm and design of measurement and control software with multi-factors were given.
阐述了信号采集电路、温度检测与实时时钟电路、Profibus-DP总线接口模块硬件和软件的设计方法，以及多参数测控软件的算法和设计。 - The level difference of these re-sults at SO is a main reflection of the level difference of UTC master clock.
So结果的水平差异主要是协调世界时主钟水平差异的反映； - Designed an oscillator which based on digital single-ended ring structure, whose main body merely consists of inverters and transfer-gates. The VCO can produce 8 clock signal which has same frequency and each adjacent phase difference is π 4.
采用全数字的单端环形压控振荡器电路，仅由反相器和传输门组成，可以产生8个频率相同的时钟信号，每个相邻信号的相位相差π4。 - Concentrator design includes the main controller, power supply circuit, memory cell, the clock module, GPRS module and interface circuit.
集中器的设计包括主控制器、电源电路、存储单元、时钟单元、GPRS模块和接口电路构成。 - Finally, this paper briefly analyzes how can the Ethernet WAN support circuit service, and summarizes the main technology challenges confronted by circuit emulation over Ethernet WAN, and particularly introduces the methods of service clock synchronization of circuit emulation over Ethernet WAN.
最后本文就广域以太网对电路型业务的支持做了简要分析，总结了广域以太网电路仿真面临的主要技术挑战，并对广域以太网电路仿真的业务时钟同步方法做了详细介绍。 - The controller has the following main modules: the clock module, display module, communication module, ADC module, key module.
本控制器具有以下几个主要功能模块：时钟模块，显示模块，通讯模块，模数转换模块，按键模块等。 - The main work include: 1. Analysis the chaos in the noise of atomic clock, thus, drew the conclusion that the operation state of atomic clock is related to environment condition. 2.
主要工作包括：1.分析了原子钟噪声中的混沌现象，表明环境条件对原子钟工作状态有很大影响。 - The main control logic of DDR2 memory, clock management, addressing mode and the implementation of trigger function under long storage mode are analyzed in detail in the thesis.
论文在高速大容量数据存储控制器的设计部分详细分析了DDR2内存的主控制逻辑，时钟管理、寻址方式和长存储模式下触发功能的设计。 - The main chip control the clock signal of FPGA, the FPGA works in slave mode.
主芯片通过SSC接口与FPGA进行通信，控制FPGA的时钟信号，FPGA工作于从模式，控制FPGA的时钟信号。 - The main task in this part focuses on detailedly analyzing the discrete process of the continuous-time model of the physical clock to build discrete-time mathematical models of oscillator clocks and the PTP protocol.
这部分的工作主要是详细分析物理时钟的连续模型的离散化过程，从而建立晶振时钟和PTP协议的离散时间数学模型。 - For example, clock problems on a main transmission line will cause enormous adjustment of clock to the main transmission line, which will impose influence over system transmission quality of transmission network and thus further exert an influence on various networks that the transmission network carries.
例如：传输干线上时钟问题会因此给整个传输系统带来大量的指针调整，这些指针调整都会对传输网的系统传输质量产生影响，进一步就影响了其上承载的各种网络。 - Using the clock generation board to generate main clock for the modules which generate pulse signals; Meanwhile Designing and realizing the synchronous clock for counting when pulse wants to be delayed. 3.
利用已有时钟板产生脉冲发生模块产生产生脉冲信号时的系统时钟；同时设计并实现同步时钟作为脉冲延迟的计数时钟。